An important aim of ongoing research in the semiconductor industry is increasing semiconductor performance while decreasing the size of semiconductor devices. One known step the industry has taken to attain this increased semiconductor performance is to implement strained silicon technology. Fortunately, strained silicon technology allows for the formation of higher speed devices.
Strained-silicon transistors may be created a number of different ways, including by introducing a dislocation loop, or excess plane of atoms, into a crystalline material. In one instance strained layers are created by forming a layer of silicon germanium (SiGe) below a silicon epitaxial layer. The average distance between atoms in the SiGe crystal lattice is greater than the average distance between atoms in an ordinary silicon lattice. Because there is a natural tendency of atoms inside different crystals to align with one another when a second crystal is formed over a first crystal, when silicon is deposited on top of SiGe, or vice-versa, the silicon crystal lattice tends to stretch or “strain” to align the silicon atoms with the atoms in the SiGe layer. Fortunately, as the electrons in the strained silicon experience less resistance and flow up to 80% faster than in unstrained silicon, the introduction of the strained silicon layer allows for the formation of higher speed devices. Problems currently exist, however, with the integration of the strained silicon technology with preexisting technologies.
Accordingly, what is needed in the art is a semiconductor device and method of manufacture therefore that experiences the benefits of strained silicon technology without experiencing its drawbacks.